ddr memory bus electrical validation and analysis software features & bene ts auto-con guration wizard guides easy setup and test con guration analyze all read/write bursts in the entire acquisition plot dqs and dq eye diagrams for reads and writes perform jedec conformance tests with pass/fail limits use chip select to qualify multi-rank measurements navigate and time stamp reads and writes in an acquired record using search and mark use pinpoint triggering, visual trigger, and dpx to quickly identify infrequent anomalies easily move between conformance-test and analysis/debug tools automatically produce consolidated reports with pass/fail information, statistical measurement results, and test-setup information on mso70000, use address/command bus to precisely qualify read and write bursts or other events on mso7000 0, perform bus timing measurements on the address/command bus applications ddr1 ddr2 ddr3 lpddr lpddr2 gddr5 option ddra accelerates the analysis, validation, and conformance testing of memory sy stems based on jedec test recommendations. a single license of ddra provides support for multiple generations of the jedec ddr st andard; beginning with ddr1, ddr2, ddr3, while including ddr derivatives lpddr, lpddr2, and gddr5. option ddra supports the common data rates in these standards alongside custom data rates up to and beyond 2133 mt/s. whether you are doing intensive signal integrity analysis or debugging a speci c memory transaction, ddra will speed your ability to trigger on and identify read and write bursts in the acquired data recor d and then perform parametric measurements on the signals of interest. ddra wizard for easy test selection and con guration the wizard consolidates tektronix experience and expertise in ddr testing into a simple, easy-to-follow test selection interface. the user selects which ddr techn ology, speed grade, and measurement group (reads, writes, clocks, address, and control lines) they are testing, using check boxes to select some or all measurements in a category. ddra can then automate oscilloscope scale selection, dq and dqs level selections, and threshold detection, then automate burst identi cation using search and mark. search and mark (for read/write measurements) data is used to identify and separate all read vs. write bursts across the entire acquisition and qualify measurement zones for use by dpojet advanced jitter and eye analysis. dpojet will generate an eye diagr am of the data and perform jedec standard measurements quali ed on read or write bursts. measurement con gurations and jedec pass/fail limits are automatically applied for the selected measurements. every edge in each identi ed burst is measured, then mea surement results are included in statistics and plots for a complete analysis of the acquired waveform.
datasheet ddr analysis menu jedec-conf orming measurements and conformance testing ddr speci cation conformance ddr jesd79e (may 2005) ddr2 jesd79-2f (november 2009) ddr3 jesd79-3d (july 2010) lpddr jesd209a (february 2009) lpddr2 jesd209-2e (april 2011) gddr5 jesd212 (december 2009) comprehensive measurements for jedec conformance testing option ddra adds a long list of jedec-speci cmeasurementstothe rich toolset of generic jitter, timing, and signal-quality measurements already present in dpojet. in addition to the measurements shown below (for ddr3 in this example), option ddra also covers other application standards like ddr1, ddr2, lpddr, lpddr3, and gddr5. ddra also performs de-rating of setup and hold pass/fail limits based on the result of slew rate measurements, as stipulated by jedec in the test specs for ddr2 and ddr3 (jesd79-2f, jes d79-3d as of this writing). easily s witch between conformance testing and adva nced debug tools ddra gives you the option to easily switch between conformance testing and adva nced analysis and debug modes. the power of the dpojet analysis engine allows you exibility to recon gure existing measurements or add new measurements not speci cally required by jedec and to create new user-speci ed test limits. you can also use features like logging, lters, histograms, and time trends in addition to the information produced by the ddra wizard. fast fault identi cation using pinpoint ? triggers and dpx technology in addi tion to all of the measurement and analysis tools that ddra offers, you can use pinpoint ? triggering and dpx ? to nd infrequent signal events. pinpoint ? triggering allows you to trigger on reads or writes so that only relevant bursts can be shown. once you have set the hardware triggering on a read or write condition, you can use dpx ? , the industry?s highest waveform acquisition rate for signal integrity testing and to determine speci c ddr read/write signal characteristics. dpx ? enables quick identi cation of infrequent events by using a color-graded display to see both frequent and infrequent waveform events, such as areas where there is bus contention, re ections, or system timing issues. new visual trigger feature now adds additional tools for setting precise trigger conditions to capture speci c bit patterns or other waveform events, based on keep-in and keep-out ar eas. jedec measurements supported for ddr3 write bursts clock(diff) vix(ac)dqs data eye width tch(abs) vseh(ac)dqs# data eye height tch(avg) vseh(ac)dqs differential dqs tck(abs) vseh(dqs#) inputslew-diff-fall(dqs) tck(avg) vseh(dqs) inputslew-diff-rise(dqs) tcl(abs) vsel(ac)dqs# tdh-diff(base) tcl(avg) vsel(ac)dqs tdh-diff(derated) tdvac(ck) vsel(dqs#) tdqsh terr vsel(dqs) tdqsl tjit(cc) dqs (single ended, read) tdqss-diff tjit(duty) ac-overshootarea(dq) tds-diff(base) tjit(per) ac-undershootarea(dq) tds-diff(derated) clock(single ended) ac-overshoot(dq) tdsh-diff ac-overshoot(ck#) ac-undershoot(dq) tdss-diff ac-overshoot(ck) ac-overshootarea(dqs) tdvac(dqs) ac-overshootarea(ck#) ac-undershootarea(dqs) single ended dqs ac-overshootarea(ck) ac-overshoot(dqs) tdipw-se ac-undershoot(ck#) ac-undershoot(dqs) tdqss-se ac-undershoot(ck) ac-overshootarea(dqs#) tdsh-se ac-undershootarea(ck#) ac-undershootarea(dqs#) tdss-se ac-undershootarea(ck) ac-overshoot(dqs#) slew rate dq vix(ac)ck ac-undershoot(dqs#) slew rate-hold-rise(dq) vseh(ac)ck# precharge slew rate-hold-fall(dq) vseh(ac)ck trp(act) slew rate-setup-rise(dq) vseh(ck#) trp(mrs) slew rate-setup-fall(dq) vseh(ck) address/command measurements twpre vsel(ac)ck# ac-overshoot twpst vsel(ac)ck ac-overshootarea read bursts vsel(ck#) ac-undershoot data eye width vsel(ck) ac-undershootarea data eye height dqs(single ended) inputslew-diff-fall(ck) differential dqs ac-overshootarea(dq) inputslew-diff-rise(ck) srqdiff-fall(dqs) ac-undershootarea(dq) slew rate-hold-fall(addr/cmd) srqdiff-rise(dqs) ac- overshoot(dq) slew rate-hold-rise(addr/cmd) tdqsck-diff ac-undershoot(dq)tdsh slew rate-setup-fall(addr/cmd) tdqsq-diff ac-overshoot(dqs#) slew rate-setup-rise(addr/cmd) tqh ac-overshoot(dqs) tih(base) tdvac(dqs) ac-overshootarea(dqs#) tih(derated) srqdiff-fall(ck) ac-overshootarea(dqs) tipw-high srqdiff-rise(ck) ac-undershoot(dqs#) tipw-low trpre ac-undershoot(dqs) tis(base) tpst ac-undershootarea(dqs#) tis(derated) ac-undershootarea(dqs) 2 www.tektronix.com
ddr memory bus electrical validation and analysis software additional capabilities using a performance mso (mixed-signal oscilloscope) the mso70000 series performance msos allow you to probe more signals on the ddr bus and to trigger on and view speci c bus events. up to 16 digital channels can be used to view logic states of command and address signals such a s ras, cas, we, ce, cs, etc. signal integrity of these 16 inputs can be analyzed using the icapture? multiplexing feature, which allows any of the digital input signals to be internally routed to one of the scope?s four analog channels. measurements involving command-bus cycle timing can also be analyzed using the bus-decode features of the mso and ddra software. full bus analysis using logic analyzer and oscilloscope when full protocol analysis or probing of the entire memory bus is required, a logic analyzer can provide this additional capability. the tla7000 series logic analyzers can also be linked with tektronix oscilloscopes to provide an integrated test setup using tools such as icapture mentioned above. this eliminates the need for double probing and allows full analog capture of any signals probed by the logic analyzer. in addition, the iview? display interface allows transfer of the oscilloscope data to the logic analyzer display, so that data from both instruments are analyzed and time-aligned on one display screen. characteristics bandwidth recommendations for each ddr standard ddr type maximum data rate (jedec) clock rate 5th harmonic of clock max se slew rate (jedec) typical sign al swing oscilloscop e rise time 10% - 90%* 1 recommended oscilloscope bw* 2 ddr 400 mt/s 200 mhz 1ghz 5v/ns 1.8 v 89 ps 4ghz ddr2 800 mt/s 400 mhz 2ghz 5v/ns 1.25 v 62 ps 6ghz ddr3 2133 mt/s 1066 mhz 5.3 ghz 5 v/ns 1.0 v 49 ps 8ghz gddr5 5 gt/s 2.5 ghz 12.5 ghz n/a 0.8 v 18 ps 20 ghz* 3 * 1 for 3% maximum error on rise-time measurement. * 2 for less stringent applications, a one-step reduction in scope bandwidth may be acceptable. * 3 basedon5gt/ssystem;lowerbwscopemaysuf ce for lower data rates. ordering information ddra ddr memory bus electrical validation and analysis oscilloscope software. to order on a new dpo5000, mso5000, dpo7000, dpo70000, dsa70000* 4 , or mso70000 series: order descrip tion opt. ddra preinstall on a new dpo5000* 5 , mso5000* 5 , dpo7000* 5 , dpo70000* 5 , dsa70000, or mso70000* 5 series oscilloscope dpofl-ddra ddr memory technology analysis package ? floating license * 4 note: opt. dja and asm are standard on the dsa70000 series oscilloscopes. * 5 note: opt. asm (advanced event search and mark) and opt. dja (dpojet) are required. to upgrade an existing dpo5000, mso5000, dpo7000, dpo70000, dsa70000, or mso70000 series: order descript ion dpo-up ddra upgrade to option ddra (requires opt. asm and dja) dpo-up djae upgrade mso/dpo5000 series with dpojet jitter and eye diagram analysis (opt. dja) dpo-up djam upgrade dpo7000 with dpojet jitter and eye diagram analysis (opt. dja) dpo-up djah upgrade dpo70404 - dpo70804 or mso70404 - mso70804 with dpojet jitter and eye diagram analysis (opt. dja) dpo-up djau upgrade dpo71254 - dpo73304 or mso71254 - mso72004 with dpojet jitter and eye diagram analysis (opt. dja) dpo-up djup dja dpojet software for scopes with both tdsjit3 and tdsrte licenses note : software is supplied on the internal hard drive of the dpo5000, mso5000, dpo7000, dpo70000, dsa70000, and mso70000 series oscilloscopes. user documentation (online or user manual) is part of the oscilloscope documentation. to order a oating license for an existing dpo5000, mso5000, dpo7000, dpo70000, dsa70000, or mso70000 series: order description dpofl-ddra ddr memory technology analysis package ? floating license dpofl-dja dpojet jitter and eye diagram analysis ? floating license www.tektronix.com 3
datasheet recommended accessories order description p7500 series trimode? differential probe 020-2955-XX micro-coax tips (trimode) for p7500 probes 020-3022-xx micro-coax tips (trimode) for p7500 probes* 6 020-2954-xx socket cable for p7500 probes p6780 differential logic probe for mso70000 tdp3500 differential probe for mso/dpo5000 and dpo7000 series oscilloscopes recommended nexus technology accessories nex-ddr3mp78bsc bga interposer for ddr3 x4/x8-solder version nex-ddr3mp78bscsk bga interposer for ddr3 x4/x8-socket version nex-ddr3mp96bsc bga interposer for ddr3 x16-solder version nex-ddr3mp96bscsk bga interposer for ddr3 x16-socket version nex-ddr2mp60bsc bga interposer for ddr2 x4/x8-solder version nex-ddr2mp60bscsk bga interposer for ddr2 x4/x8-socket version nex-ddr2mp84bsc bga interposer for ddr2 x16-solder version nex-ddr2mp84bscsk bga interposer for ddr2 x16-socket version note : for more detailed information contact http://www.nexustechnology.com * 6 for use with bga interposers only. bga interposer probing solution for ddr2/ddr3 tla7000 series logic anal yzer and logic probes connec tion to the oscilloscope through analog mux. see www.tektronix.com/logic_analyzers p7500 series trimode? probe. 020-2955-XX micro-coax tips soldered to dimm. tektronix is registered to iso 9001 and iso 14001 by sri quality system registrar. product(s) complies with ieee standard 488.1-1987, rs-232-c, and with tektronix standard codes and formats. 4 www.tektronix.com
ddr memory bus electrical validation and analysis software www.tektronix.com 5
datasheet 6 www.tektronix.com
ddr memory bus electrical validation and analysis software www.tektronix.com 7
datasheet contact tektronix: asean / australa sia (65) 6356 3900 austria 00800 2255 4835* balkans, israel, south africa and other ise countries +41 52 675 3777 belgium 00800 22 55 4835* brazil +55(11)37597627 canada 1 800 833 9200 central east eu rope and the baltics +41526753777 central europe & greece +41 52 675 3777 denmark +4580881401 finland +41526 75 3777 france 00800 2255 4835* germany 00800 2255 4835* hong kong 400 8 20 5835 india 000 800 650 1835 italy 00800 2255 4835* japan 81 (3) 67 14 3010 luxembourg +41526753777 mexico, central/south america & caribbean 52 (55) 56 04 50 90 middle east, asia, and north africa +41 52 675 3777 the netherlands 00800 2255 4835* norway 800 16098 people?s rep ublic of china 400 820 5835 poland +41 52 675 3777 portugal 80 08 12370 republic of korea 001 800 8255 2835 russia & cis +7 (495) 7484900 south africa +41526753777 spain 00800 2255 4835* sweden 00800 2255 4835* switzerland 00800 2255 4835* taiwan 886 ( 2) 2722 9622 united kingdom & ireland 00800 2255 4835* usa 1 800 833 9200 * european toll-free number. if not accessible, call: +41 52 675 3777 updated 10 february 2011 for further information. tektronix maintains a comprehensive, constantly expanding collection of application notes, technical bri efs and other resources to help engineers working on the cutting edge of technology. please visit www.tektronix.com copyrigh t ? tektronix, inc. all rights reserved. tektroni x products are covered by u.s. and foreign patents, issued an d pending. information in this publication supersedes that in all previously published material. speci ca tion and price change privileges reserved. tektronix and tek are registered trademarks of tektroni x, inc. all other trade names referenced are the service marks, trademarks, or registered trademarks of their r espective companies. 28 jun 2012 55w-22329-7 www.tektronix.com
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